1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a capacitor and a fabrication process thereof.
2. Description of the Related Art
A DRAM is a high-speed semiconductor memory device that stores information in a capacitor formed therein monolithically in the form of electric charges. Thus, DRAMs are used extensively in information processing apparatuses such as a computer as a memory device.
In these days, there is a demand for a semiconductor device in which a DRAM and an analog circuit device are formed monolithically on a common semiconductor substrate. Such an analog circuit device generally includes a capacitor formed in the monolithic state.
FIG. 1 shows the construction of a conventional DRAM 10.
Referring to FIG. 1, the DRAM 10 is formed on a Si substrate 11 on which a memory cell region 10A and a peripheral region 10B are formed, wherein each of the memory cell region 10A and the peripheral region 10B includes an active region defined by a field oxide film 12. Further, in the active region defined in the cell region 10A by the field oxide film 12, there are formed polysilicon gate electrodes 13A-13C on respective gate oxide films 13a-13c as word lines WL. In the substrate 11, there are formed diffusion regions 11a-11e adjacent to the gate electrodes 13A-13C as represented in FIG. 1, wherein each of the gate electrodes 13A-13C carries a pair of side wall insulation films. This side wall insulation film may be omitted.
Similarly, there is formed a gate electrode 13D in the peripheral region 10B via a gate insulation film 13d, and diffusion regions 11f and 11g are formed in the substrate 11 adjacent to the gate electrode 13D. Further, there is formed a high-concentration diffusion region 11h in the peripheral region 10B in correspondence to a region isolated by the field oxide film 12, and there is formed a capacitor electrode 13E on the foregoing high-concentration diffusion region 11h via an intervening insulation film 13e. It should be noted that the insulation film 13e corresponds to the gate insulation film 13d of the gate electrode 13D. As a result, the insulation film 13e form, together with the capacitor electrode 13E and the diffusion region 11h, a capacitor C of the analog circuit device that is formed in the peripheral region 10B.
It should be noted that the gate electrodes 13A-13D, the word line WL, and further the capacitor electrode 13E are covered by a first interlayer insulation film 14 formed on the substrate 11 so as to continuously cover the foregoing regions 10A and 10B, and contact holes 14A-14C are formed in the interlayer insulation film 14 so as to expose the diffusion regions 11b, 11d and 11f respectively. It should be noted that the contact holes 14A-14C have respective side walls covered by side wall insulation films 14a-14c, and bit line electrodes 15A and 15B are provided on the interlayer insulation film 14 so as to cover the contact holes 14A and 14B. Further, an electrode 15C is formed on the interlayer insulation film 14 so as to cover the contact hole 14C. Thereby, the side wall insulation film 14a prevents the short-circuit between the electrode 15A and the electrode 13A in the case the position of the contact hole 14A is offset. The side wall insulation films 14b and 14c function similarly.
Further, the electrodes 15A-15C are covered by a second interlayer insulation film 16 formed on the interlayer insulation film 14, and contact holes 16A and 16B are formed in the interlayer insulation film 16 so as to expose the diffusion regions 11a and 11c in the memory cell region 10A. The contact holes 16A and 16B are formed with respective side wall insulation films 16a and 16b, and polysilicon accumulation electrodes 17A and 17B are formed on the interlayer insulation film 16 so as to cover the contact holes 16A and 16B respectively. Thereby, the side wall insulation films 16a and 16b prevent the short-circuit between the accumulation electrode 17A or 17B with the adjacent gate electrode 13A or 13B.
In the memory cell region 10A, it should be noted that the accumulation electrodes 17A and 17B are covered by a dielectric film 18, and the dielectric film 18 in turn is covered by a polysilicon opposing electrode 19. Further, the polysilicon opposing electrode 19 is covered with a third interlayer insulation film 20 that covers also the foregoing peripheral region 10B continuously, and a contact hole 20A and a contact hole 20B are formed in the interlayer insulation film 20 such that the contact hole 20A exposes the electrode 15C and such that the contact hole 20B exposes the electrode 13E. Further, electrodes 21A and 21B are formed on the interlayer insulation film 20 respectively in correspondence to the contact holes 20A and 20B. Further, interconnection patterns 21C and 21D are formed on the interlayer insulation film 20. Thereby, the accumulation electrodes 17A and 17B form, together with the dielectric film 18 thereon and the opposing electrode 19, respective memory cell capacitors.
The DRAM 10 of FIG. 1, however, has suffered from a drawback in that there tends to appear a large step height between the memory cell region 10A and the peripheral region 10B as a result of the repeated etching processes for forming the memory cell capacitors in the memory cell region 10A. Further, such a stepped part at the boundary of the memory cell region 10A and the peripheral region 10B tends to invite accumulation of irregular polysilicon residue, which may cause various unpreferable effects such as short-circuit.